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[Internet-Networkmjpg-streamer.tar

Description: 基于USB摄像头的IP监控程序,适应提供V4L2接口的linux内核-usb video capture based IP camera for linux 2.6.xx with video for linux 2 APIs
Platform: | Size: 2658304 | Author: winger | Hits:

[USB developUSB2Serial

Description: USB转TCP/IP协议帧格式代码,很全的,经过ARM9平台测试的。可以直接用!-USB switch to TCP/IP protocol frame format code, it is full, and after ARM9 platform testing. Can use!
Platform: | Size: 10240 | Author: bingliang chen | Hits:

[USB developusb2

Description: USB 2.0 IP Core for USB Interfacing
Platform: | Size: 195584 | Author: ebi | Hits:

[Driver DevelopMCB2300

Description: LPC2300系列代码,包括usb,TCP/IP等-LPC2300 series code
Platform: | Size: 1217536 | Author: 安然 | Hits:

[VHDL-FPGA-Verilogquartus_IPcore

Description: 这15个Quartus的ip核里面有AVR,I2C,sdram,arm,usb,PCI等ipcoure,相信用过ipcore的人都知道这个的重要性,尤其是在NIOS嵌入硬件以提高速度的时候,这些事非常有用的。毕竟这些事人家封装起来的,肯定比自己去编好吧,献给用Quartus的好盆友,希望对你们有用。-free ipcoure
Platform: | Size: 4793344 | Author: 林铭团 | Hits:

[VHDL-FPGA-Verilogusb1_funct_latest.tar

Description: USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Derived from my USB 2.0 Function IP core, except all the high speed support logic has been ripped out and the interface was changed from shared memory to FIFO based. A basic test bench is now included as well. It should be viewed as a starting point to write a more comprehensive and complete test bench. I expect the users of this core to have some fundamental USB knowledge and be familiar with the UTMI specification and with the general USB transceivers (e.g. from philips). If you are not familiar with these two you should check out www.usb.org and read up on this subject ...
Platform: | Size: 59392 | Author: Andrey | Hits:

[Driver DevelopCVI-5

Description: 随着人们生活水平的提高和网络的普及,安全防护越来越深入人心。视频监控技术随着计算机、编解码、网络传输技术的发展,目前正朝着数字化、智能化、IP化、网络化方向发展。一种基于简易视频头的多路图像监控系统,在CVI环境下开发的利用两个视频头(USB接口)作监控摄像机,进行视频监控。系统能实时监控场景,启动、停止、捕捉一幅图像,当有人或物体侵入监控视野内时,系统能发出警报,并可作出警处理。系统界面新颖独特,监控区灵命度可调,内嵌操作说明,同时能够播放背景音乐,任选曲目和调节音量。系统设计简单实用,界面友好美观,实现了常用功能,达到了设计目的,体现出较好的效果。-A multi-channel video surveillance system based on simple video head, CVI development environment using two video heads (USB interface) for security cameras, video surveillance.Systems can monitor in real time the scene, start, stop, and capture an image, when people or objects within the perspective of intrusive monitoring, alert system and police.
Platform: | Size: 1620992 | Author: 方可 | Hits:

[CommunicationVB_60_LAN_Sockets

Description: VB源码实现网口控制安捷伦N6700A仪器,ZIP包中包含工程等多个文件-Communication with the N6700A over LAN may be accomplished without the use of I/O libraries or drivers. In this example it is accomplished using Winsock. Dynamic Host Configuration Protocol (DHCP) is typically the easiest way to configure the Instrument for LAN communication. DHCP automatically assigns a dynamic IP address to a device on a network. See the User s Guide for more information and how to set it up on the instrument. Connect a LAN cable and verify communication. In a DOS Window, (Run-> Command from the START menu of many Windows operating systems) type ping and the IP address of the product. For further information, see the Agilent Technologies USB/LAN/GPIB Connectivity Guide, which you can download from the Agilent web site at http://www.agilent.com/find/connectivity in the section Manuals, Guides & Notifications. Once you have established communication with the product, enter the IP address in the program for an example of instrument control using socket
Platform: | Size: 7168 | Author: forest | Hits:

[SCMp32_795_tcp_III

Description: 这个是microchip tcp/ip协议栈和USB协议栈移植在PIC32MX795F512上的源代码,另外还带UCOS操作系统-This is the the Microchip tcp/ip protocol stack and the USB stack transplantation in on PIC32MX795F512 source, also with UCOS operating system
Platform: | Size: 6155264 | Author: 周政 | Hits:

[VHDL-FPGA-Verilog9b93752447d7

Description: 用verilog 写的 USB 驱动 适用于SOPC IP CORE-USB drive write verilog. For in the SOPC IP CORE
Platform: | Size: 19456 | Author: wang | Hits:

[Other Embeded programOSPlus_src

Description: OSPlus delivers many new features to OS20 and OS21. It provides a device driver infrastructure, disk management, file systems and optionally USB and TCP/IP stacks
Platform: | Size: 1185792 | Author: zscd | Hits:

[ARM-PowerPC-ColdFire-MIPSLPC176x-web

Description: keil 源文件,包含tcpip协议栈,easyweb sever-This project is migrated from Keil MCB1700 Demo code. It can run at Keil MCB1700 board with LPC17xx. Example functionality: - Clock Settings: - XTAL = 12 MHz - PLL0 = 288 MHz - CCLK = 72 MHz Due to a bug in the LPC175x family(80 pin package) that MDIO and MDC are not functioning correctly. A bit-banging on the MDIO and MDC are included in the driver. Setting MDC_MDIO_WORKAROUND to 1 will enable the bit-banging in both MDC and MDIO. For board euipped with 80-pin LPC175x, some jumper setting is necessary for EasyWEB demo. Close "E/U" jumper(near USB Device/Host) on 2 and 3. Close "E/C" jumper(Near CAN connector) on 2 and 3. The web page shows the values of analog input(AN2). This tiny webserver needs very little resources and therefore has some restrictions: - only one active TCP session at any one time - no support for fragmented IP datagrams - no buffer for TCP datagrams received in
Platform: | Size: 346112 | Author: evan | Hits:

[VHDL-FPGA-VerilogUSB2.0IP

Description: usb2.0的IP核,对于USB接口通信的FPGA设计有很大帮助,对于接口硬件的控制更为灵活。 有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware. Detailed USB2.0 protocol description
Platform: | Size: 206848 | Author: 张奎 | Hits:

[Linux-Unixci13xxx_pci

Description: linux系统上,MIPS USB设备控制器IP核心。-linux system on MIPS USB device controller IP core.
Platform: | Size: 2048 | Author: rosalyer | Hits:

[matlabfft_ly

Description: 采用MATLAB实现定点的FFT运算,但是仿真硬件结构的IP核调用以及误差产生模式,用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of the IP core simulation calls and error generation model for simulating the effects of FPGA implementation and FFT computation sources of error.
Platform: | Size: 2048 | Author: | Hits:

[Other Embeded programHow-To-Setup-on-Raspberry-Pi.txt.tar

Description: Basic Steps (Detailed below) 1. Install NOOBS. 2. login with ssh. 3. Set the network to static IP Address. 4. Set the hostname to raspbian. 5. Update and upgrade your firmware and software. 6. Increase RAM memory allocation. 7. Installed a FTP Server. 8. Installed USB library for development. 9. Install Ramlog. (Optional) 10. Install a web Server. 11. Setup Local DNS access on your PC browser. 12. Make a backup copy of the SD card using dd.
Platform: | Size: 4096 | Author: Mike | Hits:

[Internet-NetworkUsbcameraToIpcamera

Description: 使usb摄像头可以当作ip摄像头使用的小程序-Make usb camera ip camera can be used as a ipcamera
Platform: | Size: 13312 | Author: yumingshui | Hits:

[Hook apiewinlock

Description: ErtemSoft Winlock provides the following functions: Block Internet Connection Screen Lock System Information Disable keystrokes, for example: Ctrl Alt Del, Ctrl ESC, Alt Tab, Winkey Block Keyboard Hide or replace the following the desktop elements: Windows Taskbar Windows Desktop Tray icons Disable Taskbar Windows Tweak: Disable Registry Editor (Regedit) Disable Control Panel Disable Add Remove Program Disable USB Stor Write Protect USB Stor Disable Internet Explorer Options Remove "All Programs" from Start Menu Tools: Hide / Unhide Directory from Windows Change IP Address Change DNS Address Change Internet Explorer Start Page Enable IE Start Page Button Delete Temp Files Delete IE Files (Cookies, password, more). -ErtemSoft Winlock provides the following functions: Block Internet Connection Screen Lock System Information Disable keystrokes, for example: Ctrl Alt Del, Ctrl ESC, Alt Tab, Winkey Block Keyboard Hide or replace the following the desktop elements: Windows Taskbar Windows Desktop Tray icons Disable Taskbar Windows Tweak: Disable Registry Editor (Regedit) Disable Control Panel Disable Add Remove Program Disable USB Stor Write Protect USB Stor Disable Internet Explorer Options Remove "All Programs" from Start Menu Tools: Hide / Unhide Directory from Windows Change IP Address Change DNS Address Change Internet Explorer Start Page Enable IE Start Page Button Delete Temp Files Delete IE Files (Cookies, password, more).
Platform: | Size: 465920 | Author: Yavuz | Hits:

[VHDL-FPGA-Verilogwishbone

Description: Wishbone规范具有如下特点:简单、紧凑,需要很少的逻辑门 完整的普通数据据传输总线协议,包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian),接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议,允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联,包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。 相对于其他的IP核接口规范来说,Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费,并没有专利保护。基于上述优点,因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: | Size: 12288 | Author: 程浩武 | Hits:

[VHDL-FPGA-Verilog17_usb_device

Description: 基于NIOS II的USB驱动设计,在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现USB数据传输-NIOS II design is based on the USB drive, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems USB Data Transfer
Platform: | Size: 3072 | Author: ddiao | Hits:
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